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Jinwook Jung

I am a Research Staff Member at IBM Thomas J. Watson Research Center, Yorktown Heights, NY. I received the Ph.D. degree in electrical engineering from Korea Advanced Institute of Science and Technology. My current research effort focuses on VLSI physical design, design for manufacturability, and design automation of non-conventional computing systems.

Education

Experience

Research Interests

Honors and Awards

Publications

Journals

  1. Jinwook Jung, Gi-Joon Nam, Woohyun Chung, and Youngsoo Shin,“Integrated Latch Placement and Cloning for Timing Optimization,” ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 2, pp. 22:1-22:17, Feb. 2019.
  2. Jinwook Jung, Gi-Joon Nam, Lakshmi Reddy, Iris Hui-Ru Jiang, and Youngsoo Shin,“OWARU: Free Space-Aware Timing-Driven Incremental Placement with Critical Path Smoothing,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 37, no. 9, pp. 1825-1838, Sep. 2018.
  3. Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation,” IEICE Transactions on Electronics, vol. E97-C, no. 4, pp. 332–341, Apr. 2014.
  4. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM,” IEICE Transactions on Electronics, vol. E96-C, no. 4, pp. 528–537, Apr. 2013.

Conferences

  1. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, “Standard Cell Layout Design and Placement Optimization for TFET-based Circuits,” in Proceedings of the International Symposium on Circuits and Systems (ISCAS), May 2019 (to appear).
  2. Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, and Gi-Joon Nam, “DATC RDF: An Open Design Flow From Logic Synthesis to Detailed Routing,” in Proceedings of the ICCAD’18 Workshop on Open-Source EDA Technology, Nov. 2018.
  3. Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, and Gi-Joon Nam, “DATC RDF: From Logic Synthesis to Detailed Routing,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2018.
  4. Yonghwi Kwon, Jinwook Jung, Inhak Han, and Youngsoo Shin, “Transient Clock Power Estimation of Pre-CTS Netlist,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
  5. Jingon Lee, Jinwook Jung, and Youngsoo Shin, “Fast Timing Analysis of Transistor-level Full Custom Digital Circuits” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
  6. Jaewoo Seo, Jinwook Jung, and Youngsoo Shin, “A Compact Multi-Bit Flip-Flop with Smaller Height Implementation and Metal-Less Clock Routing,” in Proceedings of SPIE Advanced Lithography, Feb. 2018, pp. 105880A:1–105880A:10.
  7. Youngsoo Song, Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, “Timing Optimization in SADP Process through Wire Widening and Double Via Insertion,” in Proceedings of SPIE Advanced Lithography, Feb. 2018, pp. 105880R:1–105880R:8.
  8. Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat, Yih-Lang Li, and Gi-Joon Nam, “DATC RDF: Robust Design Flow Database,” in Proceedings of the 2017 IEEE/ACM International Conference on Computer Aided Design (ICCAD), Nov. 2017, pp. 872-873.
  9. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, “Redundant Via Insertion in SADP Process with Cut Merging and Optimization,” in Proceedings of the 25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2017, pp. 1-6.
  10. Jaewoo Seo, Jinwook Jung, Sangmin Kim, and Youngsoo Shin, “Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization,” in Proceedings of the 54th Design Automation Conference (DAC), June 2017, pp. 54:1-54:6.
  11. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, “Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning,” in Proceedings of 2017 Grate Lakes Symposium on VLSI (GLSVLSI), May 2017, pp.137-142.
  12. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, “Redundant Via Insertion in Self-Aligned Double Patterning,” in Proceedings of SPIE Advanced Lithography, Feb. 2017, pp:1014806:1-1014806:8.
  13. Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, and Yi-Lang Li “OpenDesign Flow Database: The Infrastructure for VLSI Design and Design Automation Research,” in Proceedings of the 2016 International Conference on Computer-Aided Design (ICCAD), Nov. 2016, pp. 42:1-42:6.
  14. Jinwook Jung, Gi-Joon Nam, Lakshmi Reddy, Iris Hui-Ru Jiang, and Youngsoo Shin, “OWARU: Free Space-Aware Timing-Driven Incremental Placement,” in Proceedings of the 2016 International Conference on Computer-Aided Design (ICCAD), Nov. 2016, pp. 8:1-8:8.
  15. Jinwook Jung and Youngsoo Shin, “Localized DNA Circuit Design with Majority Gates,” in Proceedings of the 12th BioMedical Circuits and Systems Conference (BioCAS), Oct. 2016, pp. 172–175.
  16. Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, “Physical Synthesis of DNA Circuits with Spatially Localized Gates,” in Proceedings of the 33rd International Conference on Computer Design (ICCD), Oct. 2015, pp. 280–286.
  17. Jinwook Jung, Dongsoo Lee, and Youngsoo Shin, “Design and Optimization of Multiple-mesh Clock Network,” in Proceedings of the 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2014, pp. 171–176.
  18. Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory and On-Chip Diagnosis Structures Delivering x91 Failure Rate Improvement,” in Proceedings of the 15th International Symposium on Quality Electronic Design (ISQED), Mar. 2014, pp. 16–23.
  19. Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, and Hiroshi Kawaguchi, “Energy-Efficient Spin-Transfer Torque RAM Cache Exploiting All-Zero-Data Flags,” in Proceedings of the 14th International Symposium on Quality Electronic Design (ISQED), Mar. 2013, pp. 216–222.
  20. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi and Masahiko Yoshimoto, “A Variation-Aware 0.57-V Set-Associative Cache with Mixed Associativity Using 7T/14T SRAM,” in Proceedings of the 11th IEEE Faible Tension Faible Consommation (IEEE FTFC), June 2012, pp. 1–4.
  21. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi and Masahiko Yoshimoto, “256-KB Associativity-Reconfigurable Cache with 7T/14T SRAM for Aggressive DVS Down to 0.57 V,” in Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems (IEEE ICECS), Dec. 2011, pp. 524–527.

Domestic Journals and Conferences

  1. Youngsoo Song, Jinwook Jung, Youngsoo Shin, “Standard Cell Layout and Placement of TFET-based Circuits,” 2018 IEIE SoC Conference, May 2018. (In Korean)
  2. Jingon Lee, Jinwook Jung, Youngsoo Shin, “Fast Timing Analysis of Full Custom Digital Circuits with Accurate Gate RC Modeling,” The 25th Korean Conference on Semiconductors, Feb. 2018. (In Korean)
  3. Inhak Han, Jinwook Jung, Youngsoo Shin, “Optimizing Timing Margin for Timing Closure, Area, and Power,” The 23rd Korean Conference on Semiconductors, Feb. 2016. (In Korean)
  4. Jinwook Jung, Youngsoo Shin, “Managing Power Consumption and Clock Skew using Mesh Clock Network with Multiple Subtrees,” The 22nd Korean Conference on Semiconductors, Feb. 2015. (In Korean)
  5. Inhak Han, Jinwook Jung, Youngsoo Shin, “Simultaneous Fixing Hold Violations of Best and Worst Corners,” The 22nd Korean Conference on Semiconductors, Feb. 2015. (In Korean)
  6. Jinwook Jung, Dongsoo Lee, Youngsoo Shin, “Design and Optimization of Mesh Clock Network with Multi-Level Clock Gating,” The 21st Korean Conference on Semiconductors, Jan. 2014. (In Korean)
  7. Yuta Kimi, Jinwook Jung, Yohei Nakata, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “Spin-Transfer Torque RAM Cache Energy Reduction using Zero-Data Flags,” Technical Report of IEICE, vol. 113, no. 1, ICD2013-10, pp. 47–52, Apr. 2013. (In Japanese)
  8. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “A Variation-Aware Low-Voltage Set-Associative Cache with Mixed-Associativity,” Technical Report of IEICE, vol. 112, no. 170, ICD2012-31, pp. 1-6, Aug, 2012. (In Japanese)
  9. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “Associativity-Variable Cache and its Margin Enhancing Feature,” in Digest of 2012 LSI and Systems Workshop, May 2012, pp. 207-209. (In Japanese)
  10. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “Associativity-Variable Cache to Adaptively Expand Operating Voltage Margin,” Technical Report of IEICE, vol. 111, no. 388, ICD2011-139, pp. 55-60, Jan. 2012. (In Japanese)
  11. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “A Low-Voltage Cache Architecture with Word-Enhancing Scheme using 7T/14T Dependable SRAM,” in Digest of 2011 LSI and Systems Workshop, May 2011, pp. 209-211. (In Japanese)

Patents

  1. Jaewoo Seo, Jinwook Jung, Youngsoo Shin, “Semiconductor Device,” Korean patent, Jan. 2018. (Application No. P2018-0005928)
  2. Jaewoo Seo, Jinwook Jung, Youngsoo Shin, “Semiconductor Device,” Korean patent, Jan. 2018. (Application No. P2018-0000818)
  3. Jinwook Jung, Frank Musante, Gi-Joon Nam, Shyam Ramji, Lakshmi Reddy, Gustavo Tellez, and Cindy S. Washburn, “Critical Path Straightening System Based On Free-Space Aware and Timing Driven Incremental Placement,” US patent. Nov. 2016. (Application No. US20180121575A1)
  4. Hiroshi Kawaguchi, Masahiko Yoshimoto, Yohei Nakata, and Jinwook Jung, “Nonvolatile Memory Cache,” Japanese patent 2014-153965.
  5. Masahiko Yoshimoto, Hiroshi Kawaguchi, Yohei Nakata, Shunsuke Okumura, and Jinwook Jung, “Low-Voltage Cache with Mixed Associativity,” Japanese patent 2014-115723.

Book Chapters

  1. Takashi Sato, Masanori Hashimoto, Shuhei Tanakamaru, Ken Takeuchi, Yasuo Sato, Seiji Kajihara, Masahiko Yoshimoto, Jinwook Jung, Yuta Kimi, Hiroshi Kawaguchi, Hajime Shimada, and Jun Yao, “Time-Dependent Degradation in Device Characteristics and Countermeasures by Design,” Chapter 6, VLSI Design and Test for Systems Dependability, Springer, 2019.
  2. Jinwook Jung, Dongsoo Lee, and Youngsoo Shin, “Design and Optimization of Multiple-Mesh Clock Network,” Chapter 3, VLSI-SoC: Internet of Things Foundations, Springer, 2015.

References

Available upon request.


Last updated: Wed Mar 6 2019